Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that ...
INTRODUCTION TO LOGIC SYNTHESIS USING VERILO
- 作者： ROBERT B. REESE
- 出版社： IG
- 出版日期： 2006-01-01
- ISBN碼： 9781598294040
- 編號： 004297852
$ 1,442 元
原價 1,518